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Feedback simulation

LarryBaxter
4-Participant

Feedback simulation

Simulating a simple analog-input digital-output feedback loop; Input is a vector of 1024 scalars representing an analog signal. It gets a one-sample-delayed output signal subtracted, then rounded to simulate ADC quantization error, then integrated once or twice. The integrator output is the system output and gets quantized to represent a DAC and fed back, forming a first-order feedback loop with a gain of 1.

Any ideas about the best way to handle this?

...Larry
14 REPLIES 14

Please don't go further. Those things are simulated via the PID Laplace. Will try tonight as there is a pile of those things in the forum as well as the PID qs in the Mathcad 11.2a install CD.

jmG

It is not too hard to do the simulation.
Mathcad is not always the best for long
simulations, where randomised data is input as a
stream and is expected to be overwritten by the
feedback (MatLab style).

For the 1024 points it is relatively easy. The
'key' bit is to define the integration method, and
to cope with the initialisation.

The performance I expect you are considering
relates to the effect of the quantisation. This
will greatly depend on the internal quantisation
of the integrator (it could be floating point for
all I know), along with the width/style of the
integrating filter (or is it a simple summation).
You probably also want to define your sampling
period, with units, along with the signal
scalings.

Jean prefers not to use units, expecting the user
to prepare the calculations correctly. I tend to
prefer to add units wherever possible so that my
mistakes jump out at me. It is a personal choice.

Philip Oakley

You might try an iterative loop:


Fred Kohlhepp
fkohlhepp@sikorsky.com
LouP
12-Amethyst
(To:LarryBaxter)

Fred's example illustrates a way to set up a discrete time system given a vector (not necessarily periodic) input.

While the sin/cos example shows integration examples, Fred's system as defined by the vector iteration does not contain any discrete integrators within the loop. The equations need to be modified for this. A digital integrator /accumulator block is defined by int(j+1)=int(j)+input(j).

I recommend drawing a good block diagram of the system you want to model, including blocks for all the delays/latencies (converters, registers,etc.). Include specific blocks where rounding/truncation takes place (converters, bit drops) to model the quantization errors. Fred's approach will include all the effects - linear, nonlinear,etc, that you choose to model.

The rounding/truncation blocks are nonlinear elements. If these effects are not significant, and the remaining elements are linear (even if discrete time), then you can use linear analysis techniques to get the transfer function. Depending on whether any continuous time blocks in the analog domain are significant (e.g., filters), this may be done in the z domain only. In the linearized model, the rounding and truncations can usually be modeled by having an independent noise source at the block input, corresponding to the quantization error. Truncation also requires an appropriate DC offset.

Also, as Philip notes, I concur in his recommendation to use units - it gives an extra level of error checking, and allows easy entry in real units without requiring manual conversions to a dimensionless form.

Lou
LarryBaxter
4-Participant
(To:LouP)

On 9/15/2009 11:38:01 AM, lpoulo wrote:

>I recommend drawing a good
>block diagram of the system
>you want to model, including
>blocks for all the
>delays/latencies (converters,
>registers,etc.). Include
>specific blocks where
>rounding/truncation takes
>place (converters, bit drops)
>to model the quantization
>errors. Fred's approach will
>include all the effects -
>linear, nonlinear,etc, that
>you choose to model.
>
Hi,

See the original block diagram.
The ANALOG signal feeds the analog summer. The summer output feeds the embedded ADC with (actually) 100ksps sample rate, integrated once or twice with 16 bit precision in software. The DAC's analog output feeds back to the summer.
I can represent the sampled analog with a 1024-element

The only effects I'd like to model are the quantizing errors of the ADC/DAC, and also look at the difference between a simple (I) loop and a PII (proportional, two integrations) loop.

I think I could use simple MathCAD vector processing except for the feedback.

Thanks for your help so far...

...L












Try this

I added a beta factor to cope with unequal ADC / DAC
lsb values

Philip Oakley

On 9/16/2009 6:04:42 PM, philipoakley wrote:
>Try this
>
>I added a beta factor to cope
>with unequal ADC / DAC
>lsb values
>
>Philip Oakley
_____________________________

Surely you have a point, but that is outside of the control loop [feedback]. In my below Marlett, just considered the PID itself and the process tracking + the noise from digitization, i.e: at the point in the rough diagram "Display".

jmG



On 9/16/2009 11:14:04 PM, jmG wrote:
>On 9/16/2009 6:04:42 PM, philipoakley
>wrote:
>>Try this
>>
>>I added a beta factor to cope
>>with unequal ADC / DAC
>>lsb values
>>
>>Philip Oakley
>_____________________________
>
>Surely you have a point, but that is
>outside of the control loop [feedback].
>In my below Marlett, just considered the
>PID itself and the process tracking +
>the noise from digitization, i.e: at the
>point in the rough diagram "Display".
>
>jmG
>
Jean
In this case beta is inside the loop. OK it is in the analog portion between the DAC and the feedback summer point, but it is still inside.

If you let beta = 1 thinks go a bit askew!

Also the integrator could include either an absolute limit (I think 16 bits was mentioned) or could have wrap around (overflow) which again would produce 'interesting' results

You will see my example just has noise as an input. In these systems it is important to balance the 'noise', the 'signal', and the ADC level, as well as sorting out the 'integrators' filter response. [Ok a plain integrator is 1/f.. but other designs are possible in place of the 'integrator']

As an aside, the recent stock market debacle is partly caused by 'lying' about how the market works [see the noise/signal/sampling comments].
In the market's case. all the stock market rules are about avoiding signal, and adding noise, especially on the time (stability) axis.

Companies are not allowed to tell anyone anything except on rare occasions (e.g. quarterly/annual reports), everything else is rumour.

They say that the market works on ideal information feedback, which any control theorist (in engineering) will tell you is unstable. You need your gain/phase margins.

The crash occured when the market did get ideal information - it became obvious to everyone it was a busted flush and everyone bailed at the same time. In the normal cut and thrust it would have been that some banks were up and some were down, but mainly folk would be guessing. But once you are a Trillion down....

Philip Oakley

>Jean
In this case beta is inside the loop<<br> __________________________

Yes Philip, one way or another we are doing the same thing. I'm modular, simple, as per what's in hand and applicable. I'm closing the loop for all to see and use: the "smart Laplace modeler", the designer, the technicians in situ, the operators and the nagging "Patron", the teacher, the learners ... and more if you want ! This attached work sheet is more comprehensive from A...Z. there will be little more added, just to reply few + questions to the "man of the trade" as he will read and digest.

Thanks for commenting, sound and well posed.

Jean

Effect of digitization in a closed control loop:

From the work above, we have in hand the noise resulting from the ADC digitization. We separate this noise for export as it may be applied to other projects. This noise from digitization is a "standard figure", it results from the ADC accuracy, to it some extra noise adds. Below, we close the loop on a CPV-PID 3 modes recursive numerical control algorithm, we can play with P, I, D.The PID numerical controller must track as closely as possible the process model C(t).

I have ignored your project description and considered only a 2^10 ADC on pure analog signal. The proposal is for 3 CPV. I don't deny an advanced "sample & hold" > 3 [Bailey had module for 5] ... For the cases where the traditional PID is unsatisfactory, the closing control algorithm would have to be designed, requiring some extra accumulated values, to the detriment of the response.

Your project is below Marlett, neat & clean, play with PID parameters. This part of the work sheet was done months ago but never posted complete whereas the matter of the collaboration was only about "Digitization". Retouched and tutorials added. Enjoy and please do not hesitate for clarification. I have ignored the "two integrations" ... integrate what and where ?

jmG

On 9/14/2009 10:48:44 AM, baxterl wrote:
>Simulating a simple
>analog-input digital-output
>feedback loop; Input is a
>vector of 1024 scalars
>representing an analog signal.
>It gets a one-sample-delayed
>output signal subtracted, then
>rounded to simulate ADC
>quantization error, then
>integrated once or twice. The
>integrator output is the
>system output and gets
>quantized to represent a DAC
>and fed back, forming a
>first-order feedback loop with
>a gain of 1.
>
>Any ideas about the best way
>to handle this?
>
>...Larry
_____________________________

You have interpreted too many things. Simulation is simulation, it means that on the physics of the system the loop is closed on some form of PID and attempting for the tuning of the system within some constrain [best time recovery, minimal OFF setpoint excursion ...]. The physical closed loop is a much different story. You will have 3, 5 measured values in hand. Those measured values are the deviation from the actual set point and the measured PV [Process variable]. At each loop scan, the pile pushes down by one value ... etc. Those values from the "sample & hold" accumulator are then passed in the PID numerical module, thus the PID module is updated constantly at each loop scan, it contains 3 or 5 "accumulated values" available for the point numerical derivative and/or the point numerical integrate. Conclusively, at each loop scan the "sample & hold" accumulator is updated, the P, I, D up dated too and a single combined PID summed to the output of the controller... the loop is closed, live and stands alone, doing the best control if all things are tuned correctly and applied correctly from the knowledge base of the designers.

What all that means is that there is no such vector of 1024 (or else 2048, 4096,,,,) vector of values, no such round OFF,,, but only one value in the decimal steps of the digitizer of the system. Your explanation is of nature to get any "man of the trade" lost !

If you have a vector of values from the DAC [Data Acquisition], and want to reconstruct the loop back and how it had reacted over the time period of the accumulation, that is possible but of no great use, of no use at all as the reconstruct does not reconstruct over the actual controlling device (generally the control valve) and the dynamics of the system.
The attached is 1/23 work sheets in Mathcad control system. You will surely need more explanations but unfortunately this forum can't replace the academic tutorial. If you have some project, better describe what it is about, rather than telling what it's doing or attempting to do.

jmG


On 9/15/2009 1:22:39 PM, jmG wrote:

>
>You have interpreted too many things.
>Simulation is simulation, it means that
>on the physics of the system the loop is
>closed on some form of PID and
>attempting for the tuning of the system
>within some constrain [best time
>recovery, minimal OFF setpoint excursion
>...]. ...
>
>jmG

Jean,
Just say that my interpretation is that we are
doing an exact representation of another discrete
system but in a controlled manner to allow
investigation of effects, most of which will be
due to the discrete time / discrete quantisation
effect type. (I may be wrong 😉

All sorts of effects can occur in such systems
that are not predicted analytically (of the longer
average style), most frequency analysis results
ignore phase as one issue I regularly see. There
may also be aliasing effects as well.

Philip Oakley

On 9/15/2009 5:12:26 PM, philipoakley wrote:
>On 9/15/2009 1:22:39 PM, jmG wrote:
>
>>
>>You have interpreted too many things.
>>Simulation is simulation, it means that
>>on the physics of the system the loop is
>>closed on some form of PID and
>>attempting for the tuning of the system
>>within some constrain [best time
>>recovery, minimal OFF setpoint excursion
>>...]. ...
>>
>>jmG
>
>Jean,
>Just say that my interpretation is that
>we are
>doing an exact representation of another
>discrete
>system but in a controlled manner to
>allow
>investigation of effects, most of which
>will be
>due to the discrete time / discrete
>quantisation
>effect type. (I may be wrong 😉
>
>All sorts of effects can occur in such
>systems
>that are not predicted analytically (of
>the longer
>average style), most frequency analysis
>results
>ignore phase as one issue I regularly
>see. There
>may also be aliasing effects as well.
>
>Philip Oakley
______________________________________

You have a valid point Philip, about transducers that can produce such "issues". Those issues would be accounted before the point derivative/integrate. Currently they are 3, 5 points sample and hold in real control systems where no transducers produce such "issues". The proposal should include a work sheet of the project, in order to exclude myself in cases there are to many unknown and "issues" to far back in my times we had no CAS.

Thanks for reading and your constant contribution.

Jean

On 9/14/2009 10:48:44 AM, baxterl wrote:
Simulating a simple analog-input digital-output feedback loop; Input is a vector of 1024 scalars representing an analog signal. It gets a one-sample-delayed output signal subtracted, then rounded to simulate ADC quantization error, then integrated once or twice. The integrator output is the system output and gets quantized to represent a DAC and fed back, forming a first-order feedback loop with a gain of 1.

Any ideas about the best way to handle this?

...Larry
________________________

You should describe the project. There not much to understand in there. Plenty of that stuff in the forum, but what is it you want to achieve, or design outside of the "man of the trade".

jmG



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