Family Table parts conflicts

[jgiannetta]

I hope someone can help me out with this problem. I've created some Family Tables for specific size smt chip caps and res. Our designer will bring a pcb assembly into Pro/E having the smt chip cap and res and the Family table will import(open) as well. The designer than will suppress the chip caps and res. Save the assy, which works and continue on. The problem comes up when he resumes those chip caps and resistors and tries to resave the Assy. Pro/E will come up with an error stating that all the instances in the Family Tables must be verified. This does not happen if he uses Hide instead of Suppress. Why is this? Is something missing from the Family Table? Does Pro/E see a suppression as a form of modification? The parts from the Family table will then show up in the Workspace as being modified when they weren't. I appreciate any help or suggestions anyone can give. We can't seem to figure out what's going on. Thanks so much for your time!
This thread is inactive and closed by the PTC Community Management Team. If you would like to provide a reply and re-open this thread, please notify the moderator and reference the thread. You may also use "Start a topic" button to ask a new question. Please be sure to include what version of the PTC product you are using so another community member knowledgeable about your version may be able to assist.

[rh-2]

Are you creating the PCB assemblies in a family table as well, or just using the family tables for the chip, cap, and resistors in the assemblies you are creating? Are your chip cap and resistor family tables verified (all instances) at the generic level and saved each time a modification is done to the chip, cap, resistor family table? Not sure how much these PCB board assemblies differ from one another, but if you have the assemblies in a family table, you can control the features in the table to turn on and off by using yes/no parameters in the assembly family table. It sounds to me like your family table files are not being verified and saved. They certainly should not be changing simply by suppressing the feature in the upper level assembly. We do this all this time with hardware (nuts, bolts, etc.) and I can not recall this happening.

[cdiaz-2]

"Jackie Giannetta" wrote:

I hope someone can help me out with this problem. I've created some Family Tables for specific size smt chip caps and res. Our designer will bring a pcb assembly into Pro/E having the smt chip cap and res and the Family table will import(open) as well. The designer than will suppress the chip caps and res. Save the assy, which works and continue on. The problem comes up when he resumes those chip caps and resistors and tries to resave the Assy. Pro/E will come up with an error stating that all the instances in the Family Tables must be verified. This does not happen if he uses Hide instead of Suppress. Why is this? Is something missing from the Family Table? Does Pro/E see a suppression as a form of modification? The parts from the Family table will then show up in the Workspace as being modified when they weren't. I appreciate any help or suggestions anyone can give. We can't seem to figure out what's going on. Thanks so much for your time!

[RussellLudwick]

To answer your question simply, yes the suppress function is an actual modification to the assembly and it affects the master representation of the model. The hide function simply affects the visibility of the part and is not an actual modification to the assembly.

This difference is similar to the difference between simplified representations and Style Views, Simplified reps are used to show different part configurations and styles is simply to control visibility states of components.